The present invention relates to a semiconductor device, in particular, a semiconductor device having a plurality of semiconductor chips and a wiring board having thereon the semiconductor chips.
One of the technologies for sealing a plurality of semiconductor chips or semiconductor packages in one package is SiP (silicon in package). For example, in SiP, a wiring board having thereon a plurality of semiconductor chips is provided as a semiconductor device. In this case, the wiring board is equipped with a main surface (first main surface) facing the semiconductor chip to be mounted thereon and a main surface (second main surface) facing a user's (customer's) board on which the semiconductor device is mounted. The first main surface is provided with a plurality of external terminals (first external terminals) to be coupled to the semiconductor chip and the second surface is provided with a plurality of external terminals (second external terminals) to be coupled to the user's board. The wiring board has a wiring layer sandwiched between the first main surface and the second main surface and a metal wiring in the wiring layer electrically couples between the first external terminals and/or between the first external terminals and the second external terminals.
For example, coupling between the first external terminals via the metal wiring enables omission of a wiring that couples between the semiconductor chips in the user's board and thereby reduction in the user's burden. In addition, it enables speed-up.
Speaking about a technology of mounting a semiconductor device on a user's board, Japanese Unexamined Patent Application Publication No. 2006-128633 and Japanese Unexamined Patent Application Publication No. 2009-4628 describe a technology of mounting a semiconductor device having a ball grid array (BGA) package structure on a printed board which is a user's board.